Digital phase-locked circuits of the above-mentioned type are used e.g. in digital data transmission networks, which may be constructed as a synchronous digital hierarchy consisting of a plurality of network elements between which data may be transmitted.
When data are transferred in an SDH system, data are positioned e.g. in a so-called STM-1 frame which consists of 270 columns with 9 bytes in each column. The first 9 columns in a frame contain overhead functions, frame lock, etc. A frame is transferred from one network element to another with a period of 125 .mu.sec. This means that all bits in the frame, which are transmitted serially, e.g. through an optical fibre, must have been transmitted after 125 .mu.sec. For this to be feasible, the bits in an STM-1 frame must be transferred with 155.520 megabits per second.
Of course, it is important that the transfer rate of the complete frame and the timing of the transmission of the individual bits of the frame correspond closely to each other. In other words, it is important that the frame transfer time of 125 .mu.sec. and the bit read-out of 155.520 megabits per second are very accurate.
Therefore, it is desirable that the above-mentioned times are observed, and if this cannot be done, then to ensure that the bit read-out rate is closely bound up with the transfer time of the frame.
It is noted in this connection that the 125 .mu.sec. are not controlled by a reference, but solely by a frequency derived from a transmission channel.